I’m an electronics enthusiast by passion, currently a Silicon Valley based professional, working in areas of digital design and computer architecture. I graduated from SUNY, Stony Brook with strong focus in Digital Design. I love contributing to products that are of use to people and the society.
2017 Annual IEEE International Systems Conference (SysCon), Montreal, QC. doi:10.1109/SYSCON.2017.7934745
Details2016 IEEE International Symposium on Technology and Society (ISTAS), Kollam. doi:10.1109/ISTAS.2016.7764274
Details2015 International Conference on Smart Sensors and Systems (IC-SSS), Bangalore. doi:10.1109/SMARTSENS.2015.7873589
DetailsDesigned and Implemented a 150 MSPS ADC‐FPGA System (Cyclone V) for sampling Ultrasonic (PZT) Signals. Task involved selection of ADC, FPGA & design of front‐end low‐noise amplifiers, impedance matching circuits for signal conditioning.
Implemented a SONY Cell Processor Architecture (SPU) Core that includes the detection of structural, data and control hazards. Involves behavioural modelling at RTL level using Verilog to simulate the instruction flow in the pipelined processor.
StarImplemented an algorithm in C++ to generate correct output of a large digital circuit. The algorithm also makes use of PODEM for Automatic Test Pattern Generation (ATPG) to find test vectors which detects all single stuck at faults in the circuits.
StarDeveloped a C++ based accelerated hardware generator (System Verilog) for performing Matrix Vector Multiplication with configurable 3 layer neural network, and an algorithm that effectively optimises the hardware for the required degree of parallelism.
StarModelled a 32 Bit MIPS-RISC Instruction Set Architecture in System C with 5 stage Pipeline, 2 level Data cache with “Least Recently Used” cache replacement policy, single precision floating point, instruction cache and parser included.
StarModelled a 3 mobile gaze tracking system with tracking sensors and a centralised server. The images are sent by server to each mobile and the gaze data is generated by the sensor and then packetised in the mobile before it sends the packetised data back to the server.
StarImplemented a model for indoor robot navigation in SystemC. Involved multiple robots being requested in an environment while avoiding collisions.
StarAn interactive health companion that we built during CEWIT Hackaton 2018 and Won the Best use of CISCO’s MERAKI AP. Whether you’re looking for a restaurant or healthier eating this is an android application that would help you find right places and deals based on your diet.
DetailsDeveloped a low cost, open source wearable device built using off the shelf sensors that captures chewing sounds and muscle contractions and in-turn monitors the users food calorie intake, rate of consumption, and binge-eating activity.
StarDeveloped a low-cost wireless intelligent two hand gesture recognition system to recognise static gestures across 8 globally used sign languages.
StarA closed loop speed control system was developed for a 12 volt DC Motor a custom designed speed sensing module. A PWM based PID algorithm was developed and implemented to minimise response time during loaded conditions.
StarDeveloped a low-cost wireless intelligent two hand gesture recognition system to recognise static gestures across 8 globally used sign languages.
StarDeveloped a low-cost glove based gesture recognition system that acts as URC (universal remote control) for multiple consumer electronic appliances. The prototype was designed ergonomically, making it highly compact and portable.
DetailsThis project was designed to introduce automatic autonomous headlight technology for the safety of motorcyclist. The Prototype was successfully designed, focusing on intelligent headlamps that react according to the rider’s facial movement.
The objective of this project was to design and fabricate a light weight vehicle which can run in Lab carrying a person of 100kgwt (Max) at 10 Kmph. The Prototype Vehicle was successfully designed and was powered solely by air, for Movement and Braking.
Built and administered a NAS coupled ML Server Workstation dedicated for research in machine learning. (RAID-Z2 with iSCSI and CIFS interface)