EDA / Design Tools
Experienced with Cadence & Synopsys simulation, synthesis, linting and formality tools. Also familiar with Xilinx Vivado for FPGA development
Proficient in System Verilog. Experienced in Python, Shell for scripting needs and C/C++ for firmware development.
Good understanding of modern compute processors. Implemented Sony Cell SPU and custom motion processor IP (Silicon). Learning RISC-V Architecture.
Familiar with Altera Cyclone V, Xilinx Zynq, Atmel Family, ARM Family, Nordic BLE’s.