Academic and Research Projects



Digital Design and VLSI
   Project 1 - ADC-FPGA Based High-Speed Customizable Data Acquisition System (150MSPS)
Designing a SONY Cell Processor Architecture (SPU) that includes the detection of structural, data and control hazards. Involves behavioral modeling at RTL level using Verilog to simulate the instruction flow in the pipelined processor.  -  [Summer Intern Project 2018]

   Project 2 - Micro-Architecture of Synergistic Processing Unit of Sony Cell (System Verilog)
Designing a SONY Cell Processor Architecture (SPU) that includes the detection of structural, data and control hazards. Involves behavioral modeling at RTL level using Verilog to simulate the instruction flow in the pipelined processor.  -  [Jan 2018 - May 2018]

   Project 3 - Logic simulation and ATPG using PODEM (C++)
Implementing an algorithm in C++ to generate correct output of a large digital circuit. The algorithm also makes use of PODEM for Automatic Test Pattern Generation (ATPG) to find test vectors which detects all single stuck at faults in the circuits.  -  [Jan 2018 - May 2018]

   Project 4 - Hardware Generation Tool for ASIC (System Verilog)
Developed a C++ based accelerated hardware generator (System Verilog) for performing Matrix Vector Multiplication with configurable 3 layer neural network, and an algorithm that effectively optimizes the hardware for the required degree of parallelism.  -  [Aug 2017 - Dec 2017]

   Project 5 - VLSI - 8-Bit Pipelined Carry Select Adder in 45nm Technology (Virtuoso, H-Spice)
Custom designed and optimized (Cadence Virtuoso Schematic & Layout) a 8-Bit pipelined carry select adder with constraints on clock frequency, power consumption, and physical area, following 45nm micron rules.  -  [Aug 2017 - Dec 2017]

   Project 6 - 32 Bit MIPS-RISC Multiprocessor Architecture (System C)
Modelled a 32 Bit MIPS-RISC Instruction Set Architecture in System C with 5 stage Pipeline, 2 level Data cache with "Least Recently Used" cache replacement policy, single precision floating point, instruction cache and parser included.  -  [Jan 2018 - Mar 2018]

   Project 7 - Modelling of a Gaze Tracking System (System C)
Modelled a 3 mobile gaze tracking system with tracking sensors and a centralized server. The images are sent by server to each mobile and the gaze data is generated by the sensor and then packetized in the mobile before it sends the packetized data back to the server.  -  [Mar 2018 - Apr 2018]

   Project 8 - Modelling of Multi Robot Indoor Navigation System (System C)
Implemented a model for indoor robot navigation in SystemC. Involved multiple robots being requested in an environment while avoiding collisions.  -  [Apr 2018 - May 2018]

Embedded Systems & IoT
   Project 9 - Fit-Foodie - An Interactive Health Companion
An interactive health companion that we built during CEWIT Hackton 2018 and Won the Best use of CISCO's MERAKI AP. Whether you’re looking for a restaurant or healthier eating this is an android application that would help you find right places and deals based on your diet.  -  [Feb 2018]

   Project 10 - Intelligent Food Intake Monitoring System
Developed a low cost, open source wearable device built using off the shelf sensors that captures chewing sounds and muscle contractions and in-turn monitors the users food calorie intake, rate of consumption, and binge-eating activity.  -  [Aug 2017 - Dec 2017]

   Project 11 - Low-Cost Device Test Bench for Non-Intrusive Load Monitoring
Developed a low-cost wireless intelligent two hand gesture recognition system to recognize static gestures across 8 globally used sign languages.  -  [Aug 2016 - May 2017]

   Project 12 - Low-cost wireless intelligent two hand gesture recognition system
Developed a low-cost wireless intelligent two hand gesture recognition system to recognize static gestures across 8 globally used sign languages.  -  [Jan 2016 - Oct 2016]

   Project 13 - Low Cost Smart Glove for Universal Control of IR Devices
Developed a low-cost glove based gesture recognition system that acts as URC (universal remote control) for multiple consumer electronic appliances. The prototype was designed ergonomically, making it highly compact and portable.  -  [May 2016 - Oct 2016]

   Project 14 - Closed Loop Speed Control System
A closed loop speed control system was developed for a 12 volt DC Motor a custom designed speed sensing module. A PWM based PID algorithm was developed and implemented to minimise response time during loaded conditions.  -  [Sept 2015 - Dec 2015]

   Project 15 - Intelligent Smart Helmets for Automatic Control of Headlamps
This project was designed to introduce automatic autonomous headlight technology for the safety of motorcyclist. The Prototype was successfully designed, focusing on intelligent headlamps that react according to the rider’s facial movement.  -  [Mar 2015 – Sept 2015]

Other Projects
   Project 16 - Demand Side Management For A Campus Infrastructure
Simulations were carried out for a university campus incorporating a load shifting DSM technique using Genetic Algorithm to effectively manage loads and maximize the usage of existing renewable assets treating them as local grid to achieve substantial savings in cost.  -  [Dec 2015 - Mar 2016]

   Project 17 - Low-Cost Machine Learning Server with Network Attached Storage
Built and administered a NAS coupled ML Server Workstation dedicated for research in machine learning. (RAID-Z2 with iSCSI and CIFS interface)  -  [Jan 2017 - May 2017]

   Project 18 - Compressed Air Driven Vehicle
The objective of this project was to design and fabricate a light weight vehicle which can run in Lab carrying a person of 100kgwt (Max) at 10 Kmph. The Prototype Vehicle was successfully designed and was powered solely by air, for Movement and Braking.  -  [Jan 2013 - Mar 2013]